Satya Sai Pavan Kumar Doddi

Masters student in Microelectronics and VLSI Design at the University of Hyderabad with proven experience in FPGA implementation, hardware-software co-design, and digital system optimization. Experienced in developing embedded systems using Verilog and C/C++, and building ML pipelines for prediction tasks using Python. Previously worked as an Associate Engineer at Virtusa, where I worked on automation scripts and system monitoring tools that improved testing accuracy and system reliability. Passionate about advancing VLSI design, embedded systems, and intelligent hardware solutions for real-world applications such as smart agriculture and battery health diagnostics. Seeking roles in VLSI design, FPGA development, or system validation.